1. Field of the Invention
The present invention relates to a method for driving a solid-state imaging apparatus that is configured so as to obtain two-dimensional image signals by reading out signal charges that have been accumulated in a plurality of photoelectric conversion portions arranged in matrix form, and the solid-state imaging apparatus.
2. Description of Related Art
A solid-state imaging apparatus constitutes an imaging portion of a video camera or digital camera, or an image recognition portion of a facsimile or image scanner. CCD (charge coupled device) image sensors are used widely as imaging elements.
A planar structure of a conventional solid-state imaging apparatus using a CCD image sensor is described with reference to a conceptual diagram in FIG. 19. Numeral 1 refers to a photodiode forming a photoelectric conversion portion, and a plurality of such photodiodes are arranged in matrix form. An imaging region 3 is formed such that vertical CCDs 2 are arranged between the columns of the photodiodes 1. Charges accumulated in the photodiodes 1 are read-transferred to the vertical CCDs 2, and transferred in parallel by the vertical CCDs 2 in the vertical direction toward a horizontal CCD 4.
Thus, signal charges corresponding to one scanning line are read-transferred sequentially from the plurality of vertical CCDs 2 to the horizontal CCD 4. Charges that have reached the horizontal CCD 4 are transferred in the horizontal direction, converted into a signal voltage by a charge detection portion 5, amplified by an output amplifier 6, and then derived as an imaging signal output OUT. A solid-state imaging element 7 constituted by the components described above is formed on an n-type substrate 75. The imaging output undergoes signal processing at a signal processing portion 30.
Transfer from the vertical CCDs 2 is driven by, for example, four phase transfer clocks φV1, φV2, φV3, and φV4 that are supplied from a timing generating circuit 8. Thereby, each portion corresponding to one scanning line in signal charges read out by the vertical CCDs 2 is transferred sequentially in the vertical direction during a horizontal blanking period. Transfer from the horizontal CCD 4 is driven by, for example, two phase horizontal transfer clocks φH1 and φH2. Thereby, signal charges corresponding to one scanning line are transferred sequentially in the horizontal direction during a horizontal scanning period after the horizontal blanking period.
The n-type substrate 75 is grounded via a resistor 11, and a reference voltage generating circuit 9 is connected via a diode 10 at the node between the n-type substrate 75 and the resistor 11. A reference voltage generated by the reference voltage generating circuit 9 is applied as a substrate voltage Vsub to the n-type substrate 75. As described later, the substrate voltage Vsub is a voltage that is applied in order to determine the saturation of signal charges accumulated in the photodiodes 1.
Considering the unevenness in the height between potential barriers formed by the substrate voltage Vsub, due to manufacturing differences of CCD image sensors, the reference voltage is set to an optimum value for each of the elements (chips).
On the other hand, in CCD image sensors capable of an electronic shutter operation, a shutter pulse SP is generated by the timing generating circuit 8, the DC component of the shutter pulse SP is cut by a capacitor 12, and then the obtained pulse is applied to the n-type substrate 75. At that time, the low level of the shutter pulse SP is clamped by the diode 10 to the DC level of the reference voltage (see JP H07-284026A, for example).
FIG. 20 shows a cross-sectional view of the element taken along the line A-A in FIG. 19. A p-well region 17 is formed on the upper portion of the n-type substrate 75, and the photodiode 1 and a vertical CCD channel 2a are formed in the p-well region 17. An electrode 18 serving as a transfer electrode for the vertical CCD and as an electrode for controlling read transfer of signal charges from the photodiode 1 is formed thereon. Numeral 19 refers to an element separation region.
The thus configured element is driven by a pulse with three values, and signal charges are read-transferred from the photodiode 1 via a transfer gate region 24 to the vertical CCD channel 2a when the highest voltage is applied.
An operation for suppressing blooming in this element is described with reference to FIG. 21 showing the potential distribution along the line B-C-D in FIG. 20. The regions in FIG. 20 are shown with the same reference numbers as those of their corresponding photodiode 1, transfer gate region 24, vertical CCD channel 2a, p-well region 17, and n-type substrate 75.
The substrate voltage Vsub is applied between the p-well region 17 and the n-type substrate 75, and thus the p-well region 17 under the photodiode 1 joined with a pn junction is depleted, and a potential barrier is formed in the potential distribution indicated by the solid line.
Furthermore, the potential indicated by the solid line of the transfer gate region 24 shows a state in which signal charges are not read-transferred. When signal charges are read-transferred, the potential changes into one as indicated by the broken line. When the potential of the transfer gate region 24 changes into one as indicated by the broken line, charges of the photodiode 1 are read-transferred to the vertical CCD channel 2a, so that the photodiode 1 is depleted as indicated by a potential 25a. 
When a transfer period ends and an accumulation period is started, the potential well of the photodiode 1 becomes shallower as indicated by a potential 25b as charges are accumulated by incident light. When the potential 25b becomes lower than a potential 26a of the p-well region 17 in the potential distribution indicated by the solid line, excess charges pass through the p-well region 17 to be drained to the n-type substrate 75.
When charges are accumulated in the photodiode 1 in this manner in an amount exceeding the saturation charge amount that is determined by the potential barrier of the p-well region 17, excess charges are drained to the n-type substrate 75, and thus blooming is suppressed. When the substrate voltage Vsub is made high, the potential distribution changes into one as indicated by the broken line, and the saturation charge amount indicated by a potential 26b of the p-well region 17 is set to a small value. It is possible to obtain a blooming suppression effect that fits the characteristics of the element by setting the substrate voltage Vsub as appropriate.
However, this method for suppressing blooming has the following problem. During the periods in which signal charges are read-transferred by setting the potential of the transfer gate region 24 shown in FIG. 21 to the potential indicated by the broken line, charges generated in the photodiode 1 are accumulated in the vertical CCD channel 2a, the transfer gate region 24, and the photodiode 1 until the potential 25b based on the accumulated charges reaches the charge amount that corresponds to a potential lower than the potential 26a of the p-well region 17. However, if the potential of a barrier of an adjacent region within the vertical CCD channel 2a is higher than the potential 26a, then charges flow into the adjacent region within the vertical CCD channel 2a before excess charges flow into the n-type substrate 75. More specifically, during the periods in which signal charges are read-transferred from the photodiode 1, the blooming suppression effect is not practically achieved.
In order to achieve the blooming suppression effect even during the charge transfer periods, JP S61-26375A disclosed a configuration in which the n-type substrate 75 is given potentials that are different from each other between the periods to accumulate charges in the photodiode and the periods to read transfer charges. More specifically, the potential of the p-well region 17 is set to the low level potential 26a as in conventional cases during most of the signal charge accumulation periods, and is set to the high level potential 26b during the transfer periods. Thus, during the read transfer periods, charges that correspond to a potential shallower (lower) than the potential 26b for draining excess charges are not accumulated in the photodiode 1 but drained to the n-type substrate 75, and thus the blooming suppression effect is achieved. However, it is necessary that the potential of the barrier of the adjacent region of the vertical CCD 2 is lower than the potential 26b. 
Furthermore, for CCDs having a large number of pixels used for digital cameras or other devices, there are a full pixel mode (such as still image mode) in which image data is created by individually detecting accumulated charges of all pixels, and a pixel mixing mode (such as monitor mode and moving image mode) in which information of thinned-out lines is added, and thus the information amount is reduced, so that the frame rate is increased.
In the pixel mixing mode, driving is performed such that signal charges of a predetermined number of pixels of the same color read out by the same vertical CCD are added and mixed, and then transferred to a charge detection portion, so that image signals of one line are obtained for every predetermined interval in the vertical direction. In the pixel mixing mode, charges of a plurality of pixels are mixed, and thus the amount of charges added becomes large, so that it is necessary to restrict the amount of charges to be read-transferred so as not to exceed the transfer ability in a vertical or horizontal CCD.
For this reason, in the pixel mixing mode, control is performed such that the substrate voltage Vsub is made high, and thus charges accumulated in a photodiode are restricted, so that the amount of charges added is within a range in which transfer is not impeded. It is necessary to reduce the saturation charge amount by increasing the substrate voltage Vsub as the number of pixels whose charges are added becomes larger. However, in the element, there is a limitation regarding the voltage that can be set. More specifically, if the number of pixels whose charges are added is too large, then it is impossible to set the substrate voltage Vsub to its corresponding high voltage.
Furthermore, when control is performed such that an extremely small saturation charge amount with respect to the charge accumulating ability that is specific to the photodiode is obtained by applying a high substrate voltage Vsub during charge accumulation, the spectral characteristics and the sensitivity change and the linearity is deteriorated compared with those in a individual-transfer mode.
In the method described in JP S61-26375A, driving for the pixel mixing mode is not assumed, and thus only uniform suppression of blooming during the signal charge transfer periods is taken into consideration, and thus the method does not solve the above-described problem in driving for the pixel mixing mode.